(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a sleep mode with low power and small area and, more particularly, to a semiconductor integrated circuit including a power supply circuit having a global source line, a global ground line, and a local source line or a local ground line for operating at a reduced power dissipation with a smaller area.
(b) Description of the Related Art
A large-scale semiconductor integrated circuit (LSI) is more and more required to have a long continuous operation with a low voltage buttery drive, which is accelerated by recent developments of portable data assistants. Thus, an LSI incorporated in a portable data assistant is increasingly required to operate with reduced power dissipation, at a high speed on a reduced source voltage. In order to operate a CMOS LSI on a reduced source voltage without reduction of the operational speed, it is preferable that the CMOS LSI operate on a reduced threshold voltage for the CMOSFETs. However, it is generally known that CMOSFETs operating on a reduced threshold voltage are more liable to a penetrating current problem compared to CMOSFETs having a higher threshold voltage, the penetrating current causing higher power dissipation.
Patent Publication JP-A-6-29834 proposes an LSI capable of solving the problem penetrating current, wherein CMOSFETs operate with reduced power dissipation. Referring to FIG. 1, the proposed LSI includes logic circuits (combinational circuits) 301 and 302 having a low threshold voltage (Vth), a data storage circuit (sequential circuit) 303, having a high threshold voltage, for transferring data between the logic circuits 301 and 302, and a power source circuit having four source lines: a global source line VCC, a local source line QVCC, a global ground line VSS and a local ground line QVSS.
A switching transistor 304 is provided between the global source line VCC and the local source line QVCC, whereas a switching transistor 305 is provided between the global ground line VSS and the local ground line QVSS. The low-threshold logic circuits 301 and 302 are connected between the local source line QVCC and the local ground line QVSS for power supply, whereas the high-threshold data storage circuit 303 is connected between the global source line VCC and the global ground line VSS for power supply.
FIG. 2 shows practical configurations of the vicinity of the output stage of the low-threshold logic circuit 301 and the detail of the high-threshold data storage circuit 303 in the LSI of FIG. 2. The output stage of the low-threshold logic circuit 301 is implemented by a CMOS inverter gate including a low-threshold pMOSFET 312 and a low-threshold nMOSFET 313. The low-threshold logic circuit 301 as a whole including the output stage CMOS inverter gate and an inverter gate 311 for driving the output stage CMOS inverter gate is connected between the local source line QVCC and the local ground line QVSS.
The data storage circuit 303 is implemented by a latch circuit in this example. The latch circuit 303 includes a low-threshold inverter gate 317, a pair of high-threshold inverter gates 316 and 318, a pair of low-threshold transfer gates 314 and 315, and a pair of high-threshold pMOSFET 319 and nMOSFET 320. The high-threshold inverter gates 316 and 318 are connected directly to the global source line VCC and the global ground line VSS. The low-threshold inverter gate 317 is connected to the global source line VCC via the high-threshold pMOSFET 319, and to the global ground line VSS via the high-threshold nMOSFET 320.
In the conventional LSI as described above, leakage current is suppressed during a sleep mode by the high-threshold switching transistors 304 and 305 connected in the possible leakage path formed in the low-threshold logic circuit from the global source line VCC to the global ground line VSS. The switching transistors 304 and 305 as used herein should have a larger gate width because these switching transistors 304 and 305 pass a large source current. The larger gate width or transistor size, however, involves a large chip size for the LSI.